| 摘要 |
In a dimmer system including a CPU (1), a mode conversion switch (2), a zero crossing detector (3), a communication input port (4) and a gate drive (6), a mid-port of a variable resistance (VR1) for setting of fader signal level is connected through a mode conversion switch (SW1) with CPU (1), which scans the switch (SW1) and, if finds the present mode to be a communication mode and detects zero potential via switch (SW1), drives the timing pattern according to the data supplied from a main controller via input port (4). But if detects a certain voltage via switch (SW1), the present mode is formed to be an analog mode and the timing pattern is driven according to the voltage level input via switch (SW1).
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