发明名称 DATA COMPRESSION CODER
摘要 <p>PURPOSE:To improve quantization accuracy with respect to an input digital signal by applying quantization of a discrete cosine transformation DCT coefficient in a quantization stage decided by a main quantization step controller provided in a feedforward system and applying real time processing. CONSTITUTION:After a digital video signal is converted into a DCT coefficient at a DCT transformation circuit 12, the result is fed to an operation transformation circuit 21, from which the coefficient is read in zigzag pattern. The DCT coefficient is subjected to a predetermined delay by a delay circuit 22 and the result is fed to a quantization circuit 13 and it is quantized by a main quantization step controller 30. The data are compressed by a variable length coding circuit 14 and variable length coding processing is executed. The coding data are stored in a buffer memory 15 and smoothed. Since some processing time is required to calculate a quantization step by a quantization circuit 13, the delay circuit 1 22 is provided on a pre-stage of the circuit 13. Thus, real time processing is attained for the input digital video signal.</p>
申请公布号 JPH06253259(A) 申请公布日期 1994.09.09
申请号 JP19930032294 申请日期 1993.02.22
申请人 SONY CORP 发明人 UEDA YOSHITO;YOSHINAKA TADAAKI
分类号 H03M7/30;H04N5/92;H04N19/126;H04N19/134;H04N19/146;H04N19/152;H04N19/174;H04N19/196;H04N19/423;H04N19/60;H04N19/625;H04N19/91;(IPC1-7):H04N5/92;H04N7/133 主分类号 H03M7/30
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