发明名称 PROCESS AND MANUFACTURING TOOL ARCHITECTURE FOR USE IN THE MANUFACTURE OF ONE OR MORE METALLIZATION LEVELS ON A WORKPIECE
摘要 A semiconductor manufacturing tool configuration and corresponding process for applying one or more levels of interconnect metallization to a generally planar dielectric surface of a semiconductor workpiece with a minimal number of workpiece transfer operations between the tool sets is disclosed.
申请公布号 WO9959190(A2) 申请公布日期 1999.11.18
申请号 WO1999US10331 申请日期 1999.05.12
申请人 SEMITOOL, INC. 发明人 STEVENS, E., HENRY;BERNER, ROBERT, W.
分类号 H01L21/302;C12N15/31;H01L21/304;H01L21/306;H01L21/3065;H01L21/3213;H01L21/768;H01L37/00 主分类号 H01L21/302
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