发明名称 Volatile memory cell with interface charge traps
摘要 A semiconductor device is described, incorporating electron traps at the interface between a semiconductor substrate and a gate dielectric layer of an insulated gate field effect transistor, such device being capable of retaining charge in the electron traps for a certain time, allowing volatile memory circuits to be produced wherein each cell occupies only the area required for a single transistor.
申请公布号 US5608250(A) 申请公布日期 1997.03.04
申请号 US19940343016 申请日期 1994.11.21
申请人 SGS-THOMSON MICROELECTRONICS S.A. 发明人 KALNITSKY, ALEXANDER
分类号 H01L21/8247;G11C11/39;H01L21/8242;H01L27/10;H01L27/108;H01L29/788;H01L29/792;(IPC1-7):H01L29/76 主分类号 H01L21/8247
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