发明名称 |
Adaptive filtering scheme for sampling phase relations of clock networks |
摘要 |
An apparatus for adjusting phase relation of a plurality of clock signals in a processor. The apparatus contains a phase detection circuit that receives a plurality of clock signals and generates a first output based on a phase relation between those clock signals. A controller then adjusts the delay of the clock signals based on the first output of the phase detection circuit and a bit of a delay shift register to synchronize the clock signals within a predefined range. The controller generates a second output if the phase relation between the plurality of clock signals has changed before the adjusting of the delay of the clock signals has occurred. A noise band circuit is configured to receive the second output of the controller and adjust the predefined range in response to the receiving of the second output.
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申请公布号 |
US5990719(A) |
申请公布日期 |
1999.11.23 |
申请号 |
US19970947252 |
申请日期 |
1997.10.07 |
申请人 |
INTEL CORPORATION |
发明人 |
DAI, XIA;ORTON, JOHN THOMPSON |
分类号 |
G06F1/10;H03K5/13;H03L7/07;H03L7/081;(IPC1-7):H03K5/13;H03K5/00 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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