发明名称 METHOD FOR ETCHING LOW K DIELECTRIC LAYERS
摘要 A method of etching an organic dielectric layer (10) on a substrate (15) with a high etching rate and a high etching selectivity ratio. The organic dielectric layer (10) comprises a low k dielectric material, such as a silicon-containing organic polymer, for example, benzocyclobutene. A patterned hard mask layer (20) of silicon oxide or nitride is formed on the organic dielectric layer (10). An energized process gas comprises an oxygen-containing gas for etching the organic dielectric layer (10), a non-reactive gas for removing dissociated material to enhance the etching rate, and optionally, passivating gas for forming passivating deposits on sidewalls (90) of freshly etched features to promote anisotropic etching. Preferably, during etching, the temperature of substrate (15) is maintained at a low temperature of from about -30 DEG to +40 DEG to enhance the rate of etching of the dielectric layer. The etching method is particularly useful for forming interconnect plugs in c vias (100) etched through the organic dielectric layer (10) by a dual damascene process.
申请公布号 WO9956310(A3) 申请公布日期 2000.02.10
申请号 WO1999US07713 申请日期 1999.04.06
申请人 APPLIED MATERIALS, INC. 发明人 YU, MIN
分类号 H01L21/302;H01L21/3065;H01L21/31;H01L21/311 主分类号 H01L21/302
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