发明名称 Improvements relating to frequency and/or phase lock loops
摘要 A control loop ( 10 ) for producing an output signal with a stable nominal frequency is provided. The control loop includes inputs for reference ( 11 ) and oscillator ( 25 ) output signals, a beat frequency generator ( 12 ) for producing a signal with a frequency that is the difference between the oscillator and reference signal frequencies, an ADC ( 14 ) to convert the beat frequency to a digital beat frequency signal, an estimator ( 17 ) for estimating the frequency or phase of the beat signal, an adder ( 18 ) for combining an offset and modulation signal and the estimated frequency or phase of the beat signal into an added signal, and a DAC ( 23 ) for generating an analogue control signal for controlling the oscillator output frequency.
申请公布号 GB2413445(B) 申请公布日期 2007.08.29
申请号 GB20050016092 申请日期 2004.03.04
申请人 TAIT ELECTRONICS LIMITED 发明人 WILLIAM MARK SIDDALL
分类号 H03L7/185;H03C3/09 主分类号 H03L7/185
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