ADDRESS AND CONTROL SIGNAL TRAINING

摘要

In one form, an apparatus comprises a delay circuit and a controller. The delay circuit delays a plurality of command and address signals according to a first delay signal and provides a delayed command and address signal to memory interface. The controller performs command and address training in which the controller provides an activation signal and a predetermined address signal with first timing according to the first delay signal, and the plurality of command and address signals besides the predetermined address signal with second timing according to the first delay signal, wherein the second timing is relaxed with respect to the first timing. The controller determines an eye of timing for the predetermined address signal by repetitively providing a predetermined command on the command and address signals, varying the first delay signal, and measuring a data signal received from the memory interface.

主权项

1. An apparatus comprising:
a delay circuit for delaying a plurality of command and address signals according to a first delay signal and providing a plurality of delayed command and address signals to a memory interface; and a controller for performing command and address training in which said controller provides an activation signal and a predetermined address signal with first timing according to said first delay signal, and said plurality of command and address signals besides said predetermined address signal with second timing, wherein said second timing is relaxed with respect to said first timing, and said controller determines an eye of timing for said predetermined address signal by repetitively providing a predetermined command on said command and address signals, varying said first delay signal, and measuring a data signal received from said memory interface.