Method and apparatus for a partial-address select-signal generator with address shift

摘要

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing and using a partial-address select-signal generator with address shift. For example, in one embodiment, such means may include receiving a plurality of address lines; splitting the plurality of address lines into a first sub-set of the plurality of address lines and a remaining sub-set of the plurality of address lines; passing the first subset of the plurality of address lines to an upper processing path; passing the remaining sub-set of the plurality of address lines to a lower processing path in parallel with the upper processing path; generating intermediate code on the upper processing path from the first sub-set of the plurality of address lines and from an intermediate carry result from the remaining sub-set of the plurality of address lines on the lower processing path; passing a hot signal type to a decoding unit on the upper processing path, wherein the hot signal type designates a decode scheme; generating specific hot-signal select line code based on the intermediate code and the hot signal type; and adopting decode scheme of the hot-signal select lines according to information from the lower processing path. Structure for performing the same are further disclosed.

主权项

1. A circuit comprising:
an interface to receive a plurality of address lines; an upper processing path to receive a first sub-set of the plurality of address lines; a lower processing path to receive a remaining sub-set of the plurality of address lines in parallel with the upper processing path; an intermediate code based on the first sub-set of the plurality of address lines and an intermediate carry result from the remaining sub-set of the plurality of address lines; and a hot signal type to designate a decode scheme for a plurality of select lines generated based on the plurality of address lines; wherein the interface to receive the plurality of address lines comprises a circuit to receive “k×m” address lines, wherein “k” represents a number of addresses and “m” represents a bit width of the “k” addresses; and wherein the upper processing path to receive the first sub-set of the plurality of address lines comprises the upper processing path to receive “k×n” address lines at a code reduction unit, wherein “k” represents the number of addresses and further wherein “n” represents the bit width of the “k” addresses in which “n” is less than or equal to “m” of the “k×m” address lines received at the interface.