| 摘要 |
PROBLEM TO BE SOLVED: To provide an arithmetic processor in which a circuit scale can be reduced. SOLUTION: Bit data Ai, Bi, and Cj are inputted for executing an arithmetic operation '(A-B)×C', and the bit data Ai are outputted when the bit data Cj are a logical value '1', and the bit data Bi are outputted when the bit data Cj are a logical value '0'. This arithmetic processor is constituted of multiplexers 500-5015 which are set corresponding to each of all the combination of natural numbers (i) and (j). In this case, the bit data outputted from the multiplexers 500-5015, data obtained by shifting the complement data of 2 of the data B only by (n) bits toward the most significant bit, the data B, and carry data being carry from the lower bit are added for each bit so that the bit data outputted from the multiplexers 500-5015 can be added to the (i+j) bit.
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