| 摘要 |
A method of designing a logic circuit for implementing a predetermined boolean function defines a binary tree structure formed of transmission gate multiplexer (TGM) circuits. The TGM tree structure includes one binary stage for each input variable. A resulting logic circuit design is reduced by one or more stages to improve performance by employing selected boolean functions of the most significant bits of the input variables as input signals to a reduced tree structure. The method is applicable circuit design in all MOS-type technologies including NMOS, PMOS, CMOS, BiMOS, FET and the like.
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