| 摘要 |
PURPOSE:To easily and surely inspect the presence or absence of the failures in an address data bus connecting a RAM and a RAM to a central processing circuit. CONSTITUTION:This processor is provided with an initialization means 8 setting test data in which one of binaries is continuous and plural test addresses in which the one of the binaries where only one is continuous is inverted and successively shifted to a central processing circuit 8 and initializing all the stored data in a RAM 12 to the one of the binaries, a test setting means 8 inverting the stored data in the storage area of the RAM 12 selected individually in the test addresses every initialization to the other of the binaries by the test data to be transmitted by a data bus 10 and a RAM test means 8 successively reading the stored data from the RAM 12 by the data bus 10 every time this test setting means 8 is operated and deciding their proprieties. |
