DATA PROCESSOR AND MICROPROCESSOR

摘要

PROBLEM TO BE SOLVED: To realize a processor with high performance by making a 2nd processor execute instructions of a 2nd instruction set when a 1st processor executes a specific instruction in a 1st instruction set. SOLUTION: The microprocessor 100 uses an RISC core 106 for the execution of RISC instructions and a VLIW core 140 for the execution of VLIW instructions. An instruction fetch unit 101 outputs the address of an instruction to be executed to an instruction address bus 105. If a branch instruction (a part of RISC instruction) for the execution of VLIW instructions is generated during the execution of RISC instructions, an RISC decoding unit 114 informs the instruction fetch unit 101 of the branching generation. The VLIW instructions are read out of a VLIW table 113. A VLIW decoding unit 115 decodes the instructions to control a VLIW arithmetic unit 120 or integer arithmetic unit 119 and a floating-point unit 118 in parallel.