| 摘要 |
<p>A self-synchronizing descrambler for high bit rates having a number of parallel operating descrambler stages each of which represents the series connection of first and second modulo-2 adders and at least one shift register stage for the suppression of short periods between the first and second modulo-2 adders, a third modulo-2 adder is interposed which serves to invert at least one bit of the through going signal on the occurrence of a short. The invention can be used as an alternative to existing descramblers with the processing speed being reduced to a fraction of the previous speed, thus, permitting the use of cheaper semiconductor technology (CMOS).</p> |
