发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 <p>PURPOSE:To accomplish a high transfer rate by composing corresponding respective column outputs of a random access memory corresponding to respective steps of a shift register, and composing an input output device of plural bits to access in parallel plural columns corresponding to plural steps adjacent to the shift register. CONSTITUTION:A RAM composed of a 16K word X 4 bits is assembled with a serial shift register of 256 bits as a reading means. Data of a CPU data bus access simultaneously through an I/O1-I/O4 and the contents of RAM are transferred between shift registers and the shift register serially outputs data from a terminal SOUT with high speed by a shift clock SCLK. By such a composition, non-synchronously with a high speed reading by the shift register, a RAM side can access at randomly as an independent memory. Consequently, like a picture memory between CPU and a video display, the memory is used when a high speed serial data output and independent picture data processing from the output are necessary.</p>
申请公布号 JPS6148189(A) 申请公布日期 1986.03.08
申请号 JP19840168768 申请日期 1984.08.14
申请人 FUJITSU LTD 发明人 OGAWA JUNJI;BABA FUMIO
分类号 G11C11/41;G06F12/02;G06F12/04;G11C7/00;G11C11/34;G11C11/401 主分类号 G11C11/41
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