发明名称 |
Clock re-timing apparatus with cascaded delay stages |
摘要 |
<p>A video clock input signal (MCK) is applied to a delay line (30) comprising a cascade connection of a plurality (T1-T19) of delay elements for providing a plurality of delayed clock signals at respective taps (T1-T15) of the delay line. A selection circuit (6), responsive to a horizontal synchronizing signal (HS) supplied thereto, couples a selected one of the taps to an output for providing a delayed output clock signal (YCK) that is edge-aligned with the synchronizing signal (HS). For reducing the number of taps required to provide a given minimum delay step resolution and a given minimum total delay for delay elements which may vary in delay, from one integrated circuit to another, the taps are spaced one element apart for a first group (T1-T13) of the delay elements and are spaced more than one element apart for at least one (T13-T16; T17-T18; T19) second group of the elements. <IMAGE></p> |
申请公布号 |
EP0771105(A3) |
申请公布日期 |
1999.06.09 |
申请号 |
EP19960116666 |
申请日期 |
1996.10.17 |
申请人 |
THOMSON CONSUMER ELECTRONICS, INC. |
发明人 |
RUMREICH, MARK FRANCIS;GYUREK, JOHN WILLIAM |
分类号 |
H04N5/06;G09G5/18;H03K5/15;H03L7/00;H04N5/04;H04N5/45;(IPC1-7):H04N5/073 |
主分类号 |
H04N5/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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