发明名称 METHOD FOR CORRECTING GRAPHIC PATTERN FOR SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND METHOD FOR EXTRACTING GRAPHIC PATTERN
摘要 PROBLEM TO BE SOLVED: To eliminate the hindrance to secureness of a gate thrust amount brought by a corner rounding phenomenon at the time of fining by performing the reduction correction of a diffusion layer or the enlargement correction of a transistor gate. SOLUTION: A mask graphic pattern 101 is inputted in a recessed diffusion layer detection stage 102 and then it passes through an OPC stage 103 for performing optical proximity effect correction(OPC) that a difference between a designed graphic pattern for a mask and the photographic pattern after transfer is corrected, so that the mask graphic pattern after the OPC 104 is outputted. In the OPC stage 103, logical operation (subtraction) with the graphic pattern being output from the stage 102 is performed to a diffusion layer graphic pattern in a logical operation stage (subtraction) and the graphic pattern is outputted. As for the corrected mask graphic pattern for a semiconductor device; and the gate thrust amount is secured after transfer, and the other patterns are also the graphic pattern which can be arranged.
申请公布号 JP2000029200(A) 申请公布日期 2000.01.28
申请号 JP19980192888 申请日期 1998.07.08
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TSUJIKAWA HIROYUKI;SHIBATA HIDENORI;MUKAI KIYOSHI
分类号 G03F1/36;G03F1/68;G03F7/20;G06F17/50;H01L21/027 主分类号 G03F1/36
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