发明名称 LSI FAILURE ANALYZER AND ITS ANALYSIS METHOD
摘要 PROBLEM TO BE SOLVED: To provide an LSI failure analyzer which displays the estimated result of failure points of a logic LSI in a manner to overlap on a mask layout, and utilizes a critical area of mask layout data as information for specifying the failure points. SOLUTION: The critical area as an index of how easily the failure takes place is calculated with reference to design data and information on a foreign matter distribution at a production line. The calculated result is displayed while a mask layout display and failure point candidates are related to each other, thereby enabling supporting limiting the failure candidates.
申请公布号 JP2002156418(A) 申请公布日期 2002.05.31
申请号 JP20000351663 申请日期 2000.11.17
申请人 NEC CORP 发明人 GOTO JUNICHI
分类号 G01R31/28;G01R31/3183;G06F11/00;H01L21/66;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 主分类号 G01R31/28
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