| 摘要 |
A timer circuit that has low power consumption and a stable frequency of the output signal. Timer circuit 10 of this invention has highly stable oscillator 21, counter 22 and frequency dividing value controller 24. Highly stable oscillator 21 generates a standard signal at a prescribed frequency. Counter 22 determines the frequency ratio of the frequency of the internal signal to the frequency of the standard signal, and, corresponding to said frequency ratio, frequency dividing value controller 24 changes the frequency dividing value of frequency divider 12. Because the difference between the frequency of the internal signal and the frequency of the standard signal can be known from the frequency ratio, it is possible to perform control such that the frequency of the output signal is kept stable at a prescribed frequency. In this case, as a constitution wherein the highly stable oscillator operates intermittently, even when highly stable oscillator with high power consumption is used, it is still possible to lower the power consumption of the highly stable oscillator and to decrease the overall power consumed by the entire timer circuit.
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