发明名称 Transactional memory management techniques
摘要 Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes. Other embodiments are described and claimed.
申请公布号 US9361152(B2) 申请公布日期 2016.06.07
申请号 US201314129936 申请日期 2013.07.15
申请人 INTEL CORPORATION 发明人 Calciu Irina;Gottschlich Justin E.;Shpeisman Tatiana
分类号 G06F12/10;G06F9/46;G06F9/44;G06F12/08;G06F3/06 主分类号 G06F12/10
代理机构 代理人
主权项 1. An apparatus, comprising: a processor element; an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, execute the hardware transaction in a first hardware phase when a retry counter value is less than a retry threshold value for the first hardware phase, and to execute the hardware transaction in a second hardware phase when the retry counter value is greater than or equal to the retry threshold value for the first hardware phase but less than a retry threshold value for the second hardware phase; a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution; and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes.
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