发明名称 |
Nonvolatile semiconductor memory device |
摘要 |
According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first stacked layer structure including first to nth semiconductor layers (n is a natural number greater than or equal to 2) stacked in a first direction, and extending in a second direction, and first to nth memory cells provided on surfaces of the first to nth semiconductor layers facing a third direction. The ith memory cell (1≦i≦n) comprises a second stacked layer structure in which a first insulating layer, a charge storage layer, a second insulating layer, and a control gate electrode are stacked. The second insulating layer has an equivalent oxide thickness smaller than that of the first insulating layer. |
申请公布号 |
US9373631(B2) |
申请公布日期 |
2016.06.21 |
申请号 |
US201514932532 |
申请日期 |
2015.11.04 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
Sakuma Kiwamu;Kiyotoshi Masahiro;Fujii Shosuke |
分类号 |
H01L23/52;H01L29/792;H01L21/336;H01L21/20;H01L27/115;H01L21/02;H01L21/306 |
主分类号 |
H01L23/52 |
代理机构 |
Oblon, McClelland, Maier & Neustadt, L.L.P. |
代理人 |
Oblon, McClelland, Maier & Neustadt, L.L.P. |
主权项 |
1. A method of manufacturing a nonvolatile semiconductor memory device, the method comprising:
forming a first stacked layer structure including first to nth semiconductor layers (n is a natural number greater than or equal to 2) and first to n−1th interlayer insulating layers isolating the first to nth semiconductor layers, the first to nth semiconductor layers and the first to n−1th interlayer insulating layers stacked in a first direction perpendicular to a surface of the semiconductor substrate, the first stacked layer structure extending in a second direction parallel to the surface of the semiconductor substrate, and the jth interlayer insulating layer (1≦j≦n−1) provided between the jth and j+1th semiconductor layers; and forming first to nth memory cells provided on surfaces of the first to nth semiconductor layers facing a third direction perpendicular to the first and second directions respectively, the ith memory cell (1≦i≦n) comprising a second stacked layer structure in which a first insulating layer, a charge storage layer, a second insulating layer, and a control gate electrode are stacked on the surface of the ith semiconductor layer facing the third direction, and the second insulating layer having an equivalent oxide thickness smaller than that of the first insulating layer. |
地址 |
Tokyo JP |