Integrated backplane interconnection architecture.

摘要

A backplane, provides a physical layer level interconnection between a plurality of modules. The backplane includes a physical layer implementation of an interconnection topology incorporated within one or more integrated circuits called interconnect chips. Incorporated on the interconnect chips are interconnect drivers and interconnect receivers for the physical layer implementation of the interconnection topology. These interconnect drivers and interconnect receivers provide point-to-point links between the physical layer implementation of the interconnection topology and the plurality of modules. Each point-to-point link may include two separate point-to-point link lines, one for an interconnect driver and one for an interconnect receiver. For the bus interconnection topology, alternately, each point-to-point link may be tri-level, including only a single point-to-point link line. The interconnection topology may be, for example, a bus topology, a ring topology or a circuit switched topology.