| 摘要 |
PURPOSE:To determine automatically a low or high level of an outpt circuit of a reset state without executing it by a data latch and a complicated program control, by providing an output state determining signal generating cirucit on a semiconductor integrated circuit. CONSTITUTION:An output state determining signal generating circuit 14 is provided on a semiconductor integrated circuit, the source of the first N type IGFETQ11 of this circuit 14 is grounded, and the drain is connected to an input end of a selecting circuit 13. Also, the source of a TGFETQ12 is connected to the drain of the FETQ11, VDD is connected to the drain of the FETQ12, and an output state determining signal C of an H level is outputted by forming the FETQ12 as a depression type in the course of a manufacturing process. This determining signal C, a reset signal, and an internal data signal S are inputted to the selecting circuit 13, and the determining signal C is selected by a logical gate of the circuit 13 and outputted to an output buffer 11. In this way, a low level or a high level of an output circuit of a reset state is determined automatically without executing it by a data latch and a complicated program control. |
