| 摘要 |
PURPOSE: To allow a packet processing system circuit and a video descramble processing system circuit to use in common an A/D converter with a simple circuit configuration. CONSTITUTION: A timing signal generating circuit 32 calculates a packet superimposing period including a period when a scramble relation information packet signal is superimposed and a period Δt not providing effect onto synchronizing signals before and after the superimposing period and gives a timing signal fl representing changeover between the packet superimposing period and a video signal period to a clock changeover circuit 14. When the supplied timing signal f1 indicates the packet superimposing period, the clock changeover circuit 14 gives a clock signal c1 with (16/5)fsc from a (1605)fsc clock oscillator 15 to an A/D converter 13 as a clock signal g1 and when the supplied timing signal fl indicates the video signal period, the clock changeover circuit 14 gives a clock signal d1 with 4fsc from a 4fsc clock oscillator 16 to the A/D converter 13 as the clock signal g1. |
