SCHEDULING INSTRUCTIONS WITH DIFFERENT LATENCIES

摘要

An apparatus (30, 50) includes a clock (20) to produce pulses (25, 27) and an electronic hardware structure (10) having a plurality of rows (14, 16, 18) and one or more ports (12). Each row (14, 16, 18) is adapted to record a seperate latency vector (24, 26, 28) written through one of the ports (12). The latency vector (24, 26, 28) recorded therein is responsive to the clock (20). A method of dispatching instructions in a processor (30, 50) includes updating a plurality of latencies to a portion of rows (14, 16, 18) of a register latency table (10), and decreasing the expected latencies remaining in other of the rows (14, 16, 18) in response to a clock pulse (25, 27). The rows (14, 16, 18) of the portion correspond to particular registers (32, 33, 34).