发明名称 Clock recovery circuit and clock-recovering filter circuit
摘要 There is provided a clock-recovering filter circuit for use in a clock recovery circuit that generates a recovery clock signal from input data from an external device and a reference clock signal. The filter circuit includes: a pulse-inserting circuit which inserts pulses in a first phase-advancing signal or a first phase-delaying signal, thereby generating a second phase-advancing signal or a second phase-delaying signal; and a frequency-offset detecting circuit which detects frequency-offset data from the second phase-advancing signal and the second phase-delaying signal, the frequency-offset data representing a frequency difference between the recovery clock signal and the reference clock signal. The pulse-inserting circuit inserts pulses in accordance with the frequency-offset data when the first phase-advancing signal or the first phase-delaying signal is not input.
申请公布号 US7359474(B2) 申请公布日期 2008.04.15
申请号 US20040912654 申请日期 2004.08.04
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SHIRAISHI MIKIO
分类号 H03D3/24;H03L7/06;H03D3/18;H03L7/081;H03L7/093;H04L7/02;H04L7/033;H04N7/04 主分类号 H03D3/24
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