| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To shorten the time for inspecting a memory before shipping. <P>SOLUTION: A read circuit 100 reads k pieces (k is a natural number) of data from bit lines BL1-BLk prepared for each column of memory cells arranged in a matrix form and outputs as serial data DS. Sense amplifiers SA1-SAk are prepared for eack k bit line BL1-BLk to read the data from each bit line. A shift register 30 includes cascade-connected k flip-flops FF1-FFk for holding output of each sense amplifier SA and loads the output of each sense amplifier SA. An expected value setting section 32 stores expected value data output from the sense amplifiers SA1-SAk into corresponding k flip-flops FF1-FFk. A determination section 36 determines coincidence between the expected value data stored in respective flip-flops FF1-FFk and outputs of corresponding sense amplifiers SA1-SAk. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
