发明名称 Halbleiterverpackung mit ausgespartem Leiterrahmen und ausgesparter Leiterrahmen
摘要 The semiconductor casing comprises a flat, electrically conducting grid forming a central platform to support the semiconductor chip. Electrical connection terminals are distributed around the platform. Each has a reduced thickness section between thicker end portions, facilitating its anchorage within the insulating material used to encapsulate the chip and connection wires. The semiconductor casing comprises a flat grid made of electrically conducting material, with a front and rear surfaces, forming a central platform and extended electrical connection terminals distributed around the platform. The connection terminals (4) of the grid (2) each comprise an inner section (5) and an outer section (6), the back surfaces of these sections forming part of the back surface of the complete casing. The inner and outer sections are joined by a reduced thickness section (7), with the reduction causing an indent (8) on the rear surface. Electrical connection wires (12) link the front surface (5a) of the inner sections to the terminals of the circuit chip (11) mounted centrally on the platform of the grid.
申请公布号 DE60228168(D1) 申请公布日期 2008.09.25
申请号 DE2002628168 申请日期 2002.05.28
申请人 STMICROELECTRONICS S.A. 发明人 DIOT, JEAN-LUC
分类号 H01L23/495;H01L23/31 主分类号 H01L23/495
代理机构 代理人
主权项
地址