发明名称 Method and system for reducing volatile memory DRAM power budget
摘要 A portable device (114) includes a power source (120), a volatile memory (118) requiring refreshing to avoid data loss, and a memory management module (116). The volatile memory (118) is operably coupled to the power source (120) for power. The memory management module (116) is operably coupled to the volatile memory (118). The memory management module (116) is also adapted to refresh the volatile memory (118) at a refresh rate which causes refresh-based errors and to correct the refresh-based errors. Also disclosed is a method for reduced power consumption by a volatile memory requiring refreshing to avoid data loss in which such a volatile memory is refreshed (122) at a refresh rate. All defective bits are detected (124) at the refresh rate. An error correction code is selected (126) for correcting the defective bits.
申请公布号 US7483319(B2) 申请公布日期 2009.01.27
申请号 US20080127745 申请日期 2008.05.27
申请人 BROWN TERRY C 发明人 BROWN TERRY C.
分类号 G11C7/00 主分类号 G11C7/00
代理机构 代理人
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