VERTICAL NANOWIRE TRANSISTOR WITH AXIALLY ENGINEERED SEMICONDUCTOR AND GATE METALLIZATION

摘要

Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.

主权项

1. A vertical nanowire transistor, comprising:
a source region vertically aligned with a drain region along a longitudinal axis perpendicularly oriented to a surface plane of a crystalline substrate, the source region comprising a first semiconductor material and the drain region comprising a second semiconductor material different from the first semiconductor material; a channel region disposed between the source and drain region along the longitudinal axis, the channel region comprising a third semiconductor material different from the first and second semiconductor materials; and an annular gate electrode surrounding a sidewall of the channel region, separated by an annular gate dielectric layer.