| 发明名称 |
PERFORMANCE OPTIMIZED GATE STRUCTURES |
| 摘要 |
A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device. |
| 申请公布号 |
US2016163599(A1) |
申请公布日期 |
2016.06.09 |
| 申请号 |
US201414561550 |
申请日期 |
2014.12.05 |
| 申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHANG Paul;ONISHI Katsunori;YU Jian |
| 分类号 |
H01L21/8234;H01L29/66;H01L27/088;H01L29/45;H01L29/417;H01L21/308;H01L21/02 |
主分类号 |
H01L21/8234 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method, comprising:
forming source and drain regions for a first type device and a second type device; lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device; and performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device. |
| 地址 |
Armonk NY US |
