CLOCK PHASE ADAPTATION FOR PRECURSOR ISI REDUCTION

摘要

Systems and methods of mitigating precursor ISIs for communication channels having time-variant precursor channel responses using digital circuit designs. A phase adaptation circuit is utilized in a receiver and configured to generate a phase control signal responsive to an input signal and based on the current precursor channel response. The phase control signal controls the phase shift of a recovered clock to a position where the precursor ISI at h(−1) is minimized. The phase control signal corresponds to a “feed-forward equalization (FFE) first tap weight” obtained via a digital least-mean-square (LMS) process.

主权项

1. An electronic circuit or signal processing, said electronic circuit comprising:
a clock recovery circuit configured to generate a recovered clock signal based on an input signal, wherein said input signal comprises precursor intersymbol interferences (ISIs); and a precursor ISI reduction circuit coupled to said clock recovery circuit and configured to dynamically adapt a phase of said recovered clock signal based on a current magnitude of a precursor channel response that varies with time, wherein said precursor ISI reduction circuit comprises: a programmable delay circuit coupled to said clock recovery circuit and configured to:
dynamically advance a phase of said recovered clock signal responsive to an adaptation control signal; andgenerate an adapted clock signal; and a phase adaptation control circuit coupled to said programmable delay circuit and configured to generate said adaptation control signal.