发明名称 DYNAMIC DEEMPHASIS CIRCUIT
摘要 PURPOSE:To improve the S/N to VTR for home use, by excluding nonlinear element from a circuit giving time constant. CONSTITUTION:When an output of a compressor 23 is adjusted to a suitable level and it is subtracted from the original signal at a subtractor 24, the frequency characteristic at an output terminal 14 corresponds to the input signal levels. When the input signal level is greater, the output of the compressor 23 including much harmonic distortion is at a very small level in comparison with the input signal level, then the level of the harmonic distortion at the output of the subtractor 24 is small. When the input signal level is small, the output of the compressor 23 is equal to the input signal level, but the compression effect by the compressor 23 is small in this case, resulting that the harmonic distortion is small.
申请公布号 JPS5717240(A) 申请公布日期 1982.01.28
申请号 JP19800090529 申请日期 1980.07.04
申请人 HITACHI LTD 发明人 KONDOU KAZUO;HIROSE KOUICHI;YAMAMOTO AKIHIRO
分类号 G11B20/04;G11B20/06;H04B1/62;H04N5/922 主分类号 G11B20/04
代理机构 代理人
主权项
地址