| 摘要 |
The device comprises a random access memory portion and shift register for enabling parallel transfer of one line of data between the random access memory portion and the shift register. The shift register divided into several shift register portions. Serial input data is distributed alternately between the shift registr portions by a multiplexer. Serial output data is obtained by picking up data alternately from the register portions by the operation of another multiplexer. A transfer gate portion is inserted between the random access portion and the shift register for carrying out parallel transfer. The gate portion consists of several groups of transfer gates for enabling selective connections of input and output terminals of each stage of the shift register portions.
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