| 摘要 |
<p>PURPOSE:To halve the period of a timing clock compared with the case where one timing generator is used by employing two timing generators. CONSTITUTION:A counter 12 and the inner counter 21 of the timing generator 10 act due to the same basic clock TS, whereas the inner counter 25 of the timing generator 21 acts due to the reverse phase of the basic clock. When an asynchronizing scan clock PSiCLK is inputted with each counter acting due to the basic clock, an FF 15 is set. FFs 16 and 17 are set when a decoder 13 stands at four and one, respectively. Said clock turns out to be a synchronizing scan clock SiCLK, and supplied to the timing generators 19 and 20. When the scan clock SiCLK is inputted, an FF 24 is set. After the 1/2 period of the basic clock TS, an FF 28 is set, and the timing generators 19 and 20 start activation.</p> |
