发明名称 PHASE LOCKED LOOP AND DIGITAL PULSE-WIDTH MODULATION POWER CONTROLLER
摘要 PROBLEM TO BE SOLVED: To prevent the deterioration of input data by counting word clocks by generating high-resolution bit clocks by means of a PLL and comparatively counting word clocks and PCM data. SOLUTION: PCM digital data (a) are inputted to a digital receiver section 1 and extract word clocks (b) and the clocks (b) generate bit clocks (c) in a PLL section 2. On the other hand, quantity comparison is made by counting the digital data (a) preset in a comparing counter section 5 by using the bit clocks (c) from which full bit data are generated and the differences between the digital data (a) and the number of the full bit data are counted and outputted (d). In addition, a digital data control section 4 and an output control section 7 can be used by means of an output power setting section 6 at a generally easily handleable level by using control signals (e), and an A/D converter section 3 and the digital input are made selectable by means of a change-over switch (f). Therefore, indisputable reproducibility is obtained.
申请公布号 JP2000134944(A) 申请公布日期 2000.05.12
申请号 JP19980334875 申请日期 1998.10.21
申请人 FUJITA TAKESHI 发明人 FUJITA TAKESHI
分类号 G11B20/10;H02M7/48;H04L7/033 主分类号 G11B20/10
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