INTEGRATED CIRCUIT WITH LAYERED SUPERLATTICE MATERIAL AND METHOD OF FABRICATING SAME

摘要

A method of fabricating a layered superlattice DRAM (100) compatible with conventional silicon CMOS technology. A MOSFET (72) is formed on a silicon substrate (71). A thick layer (77D) of BPSG followed by a thin SOG layer (77E) overlies the MOSFET (72). A capacitor (80) is formed by depositing a layer (81) of platinum, annealing, depositing an intermediate layer (84) comprising a layered superlattice material, annealing, depositing a second layer (84) of platinum, then patterning the capacitor (80). Another SOG layer (86) is deposited, contact holes (106, 107) to the MOSFET (72) and capacitor (80) are partially opened, the SOG (86) is annealed, the contact holes (106, 107) are completely opened, and a Pt/Ti/PtSi wiring layer (88, 288) is deposited.