发明名称 |
Frequency dividing cicuit |
摘要 |
A frequency-dividing circuit comprises a digital accumulator capable of performing signed arithmetic and means for adding of a predetermined numerator to the content of the accumulator. Means are provided for subtracting a predetermined denominator from the content of the accumulator and further means detect if the value held in the accumulator has become zero or negative and establishing a delay setting value dependent upon the held value. Further means convert the delay setting value into a time delay inversely proportional to the magnitude of the delay setting value and the yet further means change the state of a digital output signal on expiry of the said time delay. A corresponding method is also disclosed. |
申请公布号 |
GB9618069(D0) |
申请公布日期 |
1996.10.09 |
申请号 |
GB19960018069 |
申请日期 |
1996.08.28 |
申请人 |
TECHNOLOGY PARTNERSHIP, THE PLC |
发明人 |
|
分类号 |
H03K23/66;G06F7/68 |
主分类号 |
H03K23/66 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|