| 摘要 |
A semiconductor memory device comprises a memory cell array including a plurality of memory cells, each having a data storage capacitor and a MOS transistor, arranged in rows and columns, a plurality of word lines connected to the memory cells in a direction of the rows, a row decoder for decoding a row address signal synchronized with a /RAS signal for selecting one of the word lines corresponding to an arbitrary one of the rows, a plurality of sense amplifiers, provided to have the same number as the number of the columns, for sensing data read out from the memory cells, a plurality of transfer gates connected to the sense amplifiers, a plurality of data latch circuits connected to the transfer gates, to latch the data sensed by the sense amplifiers through the transfer gates, a plurality of column selection gates connected to the data latch circuits for selecting at least one of the data latch circuits, a column decoder for decoding a column address signal for selecting an arbitrary one of the columns to switch-control the column selection gates, and a row controller controlling the row decoder to activate the one of the word lines and inactivate the same at a pre-determined timing which falls within the period after the sense amplifiers are stabilized in an activated state and before the /RAS signal is inactivated.
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