发明名称 Reduced video signal processing circuit
摘要 An input processing section reduces the content of an input video signal according to reduction ratio data, and the reduced video signal is stored in field memories. A display processing section reads a reduced video signal from the field memories to execute window display processing thereto according to video size SIZ data and video position data (X, Y). In this event, an input video clock generator, controlling a writing operation to the field memories, computes video size SIZ data from the reduction ratio data, and writes the SIZ data as a header, along with the reduced video signal, into the field memories via the input processing section. The SIZ data is read to be output to the display processing section and a display video clock generator for controlling reading.
申请公布号 US6008854(A) 申请公布日期 1999.12.28
申请号 US19960730596 申请日期 1996.10.15
申请人 SANYO ELECTRIC CO., LTD. 发明人 SHIMIZU, YUTAKA
分类号 G09G5/00;G09G5/14;G09G5/18;G09G5/36;H04N1/393;H04N5/45;(IPC1-7):H04N7/081 主分类号 G09G5/00
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