| 摘要 |
A computer system with a memory device having plural memory banks and a method of accessing a selected one of the memory banks, the memory device including local control signal generators that control timing of operations in each respective block of a memory array. Overall timing of the device is controlled by first and second global control signals generated in a command sequencer and decoder. The second global control signal is derived from a delayed version of the first signal, and both signals are applied to local control signal generators along with address bits indicating a selected block. The timing of the global signal generators is determined by row charge and discharge models. Local timing is determined by the global control signals and by local circuitry within the local control signal generators. The second global control signal drives a first portion of a sense amplifier and a delayed version of the second global signal drives a second portion of the sense amplifier. Local control signal generators include latch circuits to produce a latch output signal that activates a selected row.
|
