发明名称 Sampling flip-flop for testing digital logic at end of production line
摘要 The device has two temporary memories (918,920), each with an input and output, and three multiplexers. The first multiplexer (930) has a serial input, a parallel input, a selection input and an output connected to the first memory's input. The second multiplexer (940) has a serial input connected to that of the first multiplexer, a flop input connected to the output of the first memory, a selection input connected to that of the first multiplexer and an output connected to the input of the second memory. The third multiplexer (950) has inputs connected to the memory outputs, a control input and an output. An Independent claim is also included for a circuit with a chain of sampling flip-flops.
申请公布号 DE19927094(A1) 申请公布日期 1999.12.30
申请号 DE19991027094 申请日期 1999.06.15
申请人 NATIONAL SEMICONDUCTOR CORP., SANTA CLARA 发明人 QURESHI, FAZAL UR REHMAN
分类号 G01R31/3185;(IPC1-7):H03K5/15;G01R31/318 主分类号 G01R31/3185
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