发明名称 |
Single-chip multi-port Ethernet switch |
摘要 |
An architecture for a multi-port switching device is described having a very regular structure that lends itself to scaling for performance speed and a high level of integration. The distribution of packet data internal to the chip is described as using a cell-based TDM packet transport configuration such as a ring. Similarly, a method of memory allocation in a transmit buffer of each port allows for reassembly of the cells of a packet for storage in a contiguous manner in a queue. Each port includes multiple queues. The destination queue and port for a packet is identified in a multi-bit destination map that is prepended to the start cell of the packet and used by a port to identify packets destined for it. The architecture is useful for a single-chip multi-port Ethernet switch where each of the ports is capable of 10 Gbps data rates.
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申请公布号 |
US7289537(B1) |
申请公布日期 |
2007.10.30 |
申请号 |
US20030700385 |
申请日期 |
2003.11.03 |
申请人 |
GREENFIELD NETWORKS, INC. |
发明人 |
DEVANAGONDI HARISH R.;BELUR HARISH P.;PETERSEN BRIAN A. |
分类号 |
H04J3/24 |
主分类号 |
H04J3/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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