发明名称 MEMORY DEVICE
摘要 A memory device may include: first to Nth cell blocks; first to (N−1)th bit line sense amplifiers, of which a Kth bit line sense amplifier amplifies a potential difference between a bit line of a Kth cell block and a bit line of a (K+1)th cell block; one or more first outermost bit line sense amplifiers suitable for amplifying a potential difference between a first node and a bit line of the first cell block, wherein drivability for driving the first node is different from drivability for driving the bit line of the first cell block; and one or more second outermost bit line sense amplifiers suitable for amplifying a potential difference between a second node and a bit line of the Nth cell block, wherein drivability for driving the second node is different from drivability for driving the bit line of the Nth cell block.
申请公布号 US2016163375(A1) 申请公布日期 2016.06.09
申请号 US201514705628 申请日期 2015.05.06
申请人 SK hynix Inc. 发明人 KIM Dong-Keun
分类号 G11C11/4091;G11C11/4094;G11C11/4093 主分类号 G11C11/4091
代理机构 代理人
主权项 1. A memory device comprising: first to Nth cell blocks where N is a natural number greater than 2; first to (N−1)th bit line sense amplifiers, of which a Kth bit line sense amplifier amplifies a potential difference between a bit line of a Kth cell block and a bit line of a (K+1)th cell block, where K is a natural number from 1 to N−1; one or more first outermost bit line sense amplifiers suitable for amplifying a potential difference between a first node and a bit line of the first cell block, wherein a drivability for driving the first node is different from a drivability for driving the bit line of the first cell block; and one or more second outermost bit line sense amplifiers suitable for amplifying a potential difference between a second node and a bit line of the Nth cell block, wherein a drivability for driving the second node is different from a drivability for driving the bit line of the Nth cell block.
地址 Gyeonggi-do KR