| 摘要 |
<p>PURPOSE:To reduce the circuit scale and to operate the circuit even if the frequency of an input clock differs from that of a receiver side clock by constituting the circuit with an inverter, a multiplier circuit, an exclusive OR gate, a delay circuit, two selectors and an FF. CONSTITUTION:A receiver side clock signal and a signal being an inverted receiver side clock signal are inputted to a selector 5 to exclusively OR the receiver side clock signal and the input clock signal. Then the result is latched in the 1st FF 4 by using a clock signal whose frequency is twice that of the receiver side clock signal and the selector 5 selects a relevant clock signal from the two clock signals at the level of the result of latching. Then the said clock signal is used to latch an input data signal at an FF 6, and a selector 8 selects a data output from the output of the FF 6 and an output being the result of retarding the output of the FF 6 by a time being a half the period of the receiver side clock signal depending on the output level of the FF 4 similarly to the case with the selector 5 to recover the input data signal.</p> |
