| 摘要 |
<p>The present invention provides an efficient streamlined pipeline for a counterflow pipeline processor (110) with a renaming table (235). The counterflow pipeline (110) includes an execution pipe (220) having multiple instruction stages forming an instruction pipe (221), a plurality of result stages forming a result pipe, and a corresponding plurality of comparator/inserters. Each comparator/inserter couples an instruction stage to a corresponding result stage. The counterflow pipeline also includes a register exam stage with the renaming table (235). The renaming table has entries for associating each register value of an instruction with a unique renamed register number (RRN), thereby eliminating the need for arbitration and housekeeping (killing of stale register values), as instructions and their respective register values counterflow in the streamlined counterflow pipeline. An RRN counter, such as a modulo counter, is coupled to the renaming table and provides unique RRNs for assignment to new register values. In accordance with one embodiment of the invention, instructions are decoded and unique RRNs assigned to the source and destination operand registers. If there is no previous RRN assigned to a register operand, its register value is retrieved from a register file and inserted into the top of the result pipe. In addition, when an instruction execution produces a register result value in the execution pipe, the associated RRN and register value are inserted laterally into the result pipe. The register values and RRNs, in the form of result packages, are garnered by younger (later in program order) instructions counterflowing up the instruction pipe. <MATH></p> |
