Integrated circuit which uses a damascene process for producing staggered interconnect lines
摘要
An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.
申请公布号
US5846876(A)
申请公布日期
1998.12.08
申请号
US19960655244
申请日期
1996.06.05
申请人
ADVANCED MICRO DEVICES, INC.
发明人
BANDYOPADHYAY, BASAB;FULFORD, JR., H. JIM;DAWSON, ROBERT;HAUSE, FRED N.;MICHAEL, MARK W.;BRENNAN, WILLIAM S.