| 摘要 |
A resistance variable memory device such as e.g., a PCRAM memory device, with either a 4T (transistor) or 2T memory cell configuration and either a dual cell plate or word line configuration. The device includes additional circuitry configured to write or erase addressed cells while keeping the voltage across non-addressed cells at approximately 0V. The device also includes circuitry that reads the addressed cells in a manner that increases the sensing window without causing the potential across the cell to be greater than approximately 200 mV. The device may also sense the state of its addressed cells closer in time to when the cells are accessed, in comparison to typical sensing techniques.
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