| 摘要 |
A microprocessor having a power-saving fetch and decoding unit for fetching and decoding compressed program instructions and having a program instruction sequencer is disclosed. The microprocessor based on the inventive architecture has a power-saving fetch and decoding unit for fetching and decoding program instructions. The fetch and decoding unit has a program instruction memory which receives a sequential program instruction address addressing the next program instruction memory line which is to be read, having at least one program instruction memory line which can store an indicator flag, a long program instruction index, a short program instruction and a first source register address. A directory memory receives the long program instruction index ( 6 ) addressing the next directory memory line which is to be read. A short program instruction decoding unit for decoding the short program instruction which has been read from the program instruction memory and for providing a first program instruction counter.
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