发明名称 |
SYNCHRONOUS MEMORY |
摘要 |
A synchronous single port random access memory comprises a core 2 of memory cells 3 arranged as rows and columns. The rows are addressed by a row decoder 5 and the memory cell outputs are connected as columns to a column decoder and multiplexer 7. The decoder and multiplexes 7 selects groups of memory cells 3 from the addressed row and connects these to sense amplifiers 8. Changes in address are propagated immediately to the core 2 so that the selected memory cells 3 are connected as quickly as possible and without any fixed delays to the sense amplifiers 8. Similarly, a read clock "rclk" enables the sense amplifiers 8 immediately upon becoming active.
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申请公布号 |
CA2297878(A1) |
申请公布日期 |
2000.08.06 |
申请号 |
CA20002297878 |
申请日期 |
2000.02.03 |
申请人 |
MITEL SEMICONDUCTOR LIMITED |
发明人 |
JOHNSTON, DAVID;MARTIN, ALAN;ALBON, RICHARD |
分类号 |
G11C7/10;G11C7/22;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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